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Verilog Designer's Library

Verilog Designer's Library

Bob Zeidman

410 pages, parution le 10/06/1999

Résumé

This book organizes Verilog routines according to functionality, making it easy to locate the material you need. Each function is described by a behavioral model to use for simulation, followed by the RTL code you'll use to synthesize the gate-level implementation. Extensive test code is included for each function, to assist you with your own verification efforts.

Coverage includes:

  • Essential Verilog coding techniques
  • Basic building blocks of successful routines
  • State machines and memories
  • Practical debugging guidelines

Although Verilog Designer's Library assumes a basic familiarity with Verilog structure and syntax, it does not require a background in programming. Beginners can work through the book in sequence to develop their skills, while experienced Verilog users can go directly to the routines they need. Hardware designers, systems analysts, VARs, OEMs, software developers, and system integrators will find it an ideal sourcebook on all aspects of Verilog development.

Author info
Bob Zeidman is the president of Zeidman Consulting, a hardware and software contract development firm in Silicon Valley, CA. He has designed ASICs, FPGAs, and PC boards for RISC-based parallel processor systems, laser printers, network switches and routers, and other real time systems. His clients have included Apple Computer,Cisco Systems, Ricoh Systems, and Texas Instruments. He has written several technical papers on hardware and software design methods, and has taught courses at engineering conferences throughout the country. He holds an MS from Stanford University and two Bachelor's degrees from Cornell University.

Caractéristiques techniques

  PAPIER
Éditeur(s) Prentice Hall
Auteur(s) Bob Zeidman
Parution 10/06/1999
Nb. de pages 410
Format 18,5 x 24,2
Poids 850g
EAN13 9780130811547

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