A Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Sy
Slobodan Mijalkovic
319 pages, parution le 14/09/2022
Résumé
With the introduction of language extensions to support compact device modeling, the Verilog-A has become today de facto standard language in the electronics industry for coding compact models of active and passive semiconductor devices. You'll gain an in depth look at how analog circuit simulators work, solving system equations, modeling of components from other physical domains, and modeling the same physical circuits and systems at various levels of detail and at different levels of abstraction.
All industry standard compact models released by Si2 Compact Model Coalition (CMC) as well as compact models of emerging nano-electronics devices released by New Era Electronic Devices and Systems (NEEDS) initiative are coded in Verilog-A. This book prepares you for the current trends in the neuromorphic computing, hardware customization for artificial intelligence applications as well as circuit design for internet of things (IOT) will only increase the need for analog simulation modeling and make Verilog-A even more important as a multi-domain component-oriented modeling language.
Let A Practical Guide to Verilog-A be the initial step in learning the extended mixed-signal Verilog-AMS hardware description language.
What You'll Learn
- Review the hardware description and modeling language Verilog-A in its most recent standard formulation.
- Code new compact models of active and passive semiconductor devices as well as new models for emerging circuit components from different physical disciplines.
- Extend the application of SPICE-like circuit simulators to non-electronics field (neuromorphic, thermal, mechanical, etc systems).
- Apply the initial steps towards the extended mixed-signal Verilog-AMS hardware description language.
Electronic circuit designers and SPICE simulation model developers in academia and industry. Developers of electronic design automation (EDA) tools. Engineers, scientists and students of various disciplines using SPICE-like simulators for research and development.
Chapter 2: The Lexical Basis of Verilog-AChapter Goal: Introducing Verilog-A lexical tokens, token separators as well as basic token groups and token containers.
Chapter 3: Basic Types and ExpressionsChapter Goal: Introducing integer, real and string data types and how expressions are assembled for different types using operators.
Chapter 4: Nets and SignalsChapter Goal: Introducing the concept of nets and signals defined by nature and net_discipline types.
Chapter 5: Modules and NetlistsChapter Goal: Introducing modules, as basic units of hierarchy in Verilog-A language, and their instantiation in SPICE and Verilog-A netlists.
Chapter 6: Parameters and ParamsetsChapter Goal: Introducing the concept of parameters, customization of modules by passing parameters into a module at instantiation and the concept of instance and model parameters defined via paramsets.
Chapter 7: Branch Contribution StatementsChapter Goal: Introducing the concept of analog branch assignments and signal access mechanisms.
Chapter 8: Procedural StatementsChapter Goal: Introducing analog procedural block and procedural control statements.
Chapter 9: Derivative and Integral OperatorsChapter Goal: Detailed description of analog functions used to perform differentiation and integration in time.
Chapter 10: Built-in Mathematical FunctionsChapter Goal: Define all Verilog-A standard mathematical function.
Chapter 11: User Defined FunctionsChapter Goal: Describe how to write modular, maintainable and reusable models in Verilog-A using user defined functions.
Chapter 12: Analog Filter FunctionsChapter Goal: Introducing Verilog-A time and frequency domain filter functions and their usage with constant and dynamic arguments.
Chapter 13: Look-Up Table ModelsChapter Goal: Describing how to create a multidimensional interpolation lookup-up table models in Verilog-A
Chapter 14: Small Signal and Noise SourcesChapter Goal: Introducing Verilog-A functions supporting small signal and noise analysis in SPICE simulators.
Chapter 15: EventsChapter Goal: Introducing methods to control analog behaviour of the component models in Verilog-A.
Chapter 16: Input and OutputChapter Goal: Describe methods and functions to read and write formatted data.
Chapter 17: Simulator Query and Control MethodsChapter Goal: Describing the methods to access the simulator kernel parameters in the Verilog-A model.
Chapter 18: AttributesChapter Goal: Introducing attributes as a mechanism for specifying properties about objects, statements and groups of statements in the Verilog-A source that can be used by the simulator.
Chapter 19: Compiler DirectivesChapter Goal: Introducing compiler directives that dictate Verilog-A compiler behaviour in a pre-processingcompilation phase.
Chapter 20: SPICE CompatibilityChapter Goal: Describes the degree of compatibility with SPICE-like simulators which Verilog-A provides and the approach taken to provide that compatibility.
Dr. Mijalkovic has authored 50 cited publications including the monograph "Multigrid Methods for Process Simulation" published by Springer. In the period 2002-2006 he has set and chaired four editions of "Compact Modeling for RF Application (CMRF)" workshops that strongly contributed to the acceptance of Verilog-A as a standard compact modeling language. He is a senior Member of IEEE and currently a member of the IEEE EDS Compact Modeling Committee.
Caractéristiques techniques
| PAPIER | |
| Éditeur(s) | Apress |
| Auteur(s) | Slobodan Mijalkovic |
| Parution | 14/09/2022 |
| Nb. de pages | 319 |
| EAN13 | 9781484263501 |
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