Embedded Microprocessor Systems Design

Contents

Preface                                            xi
  CHAPTER 1  Introduction                          1
    1.1  Microprocessors and Embedded Systems      3
    1.2  Diverse Applications                      5
    1.3  Common System Structure and Operation     9
    1.4  Embedded System Design                    11
    1.5  The 80C188EB Microprocessor and the       16
    80x86 Family
    1.6  Organization of this Text                 20
    1.7 Summary                                    22
  CHAPTER 2  Register View of a Simple             23
  Microprocessor System
    2.1  Memory Cells                              24
    2.2  Storage Registers                         27
    2.3  Data Transfer Between Registers           31
    2.4  Register View of a Memory Subsystem       35
    2.5  Register View of I/O Subsystems           36
    2.6  Operational Registers                     38
    2.7 Register View of a Simple Microprocessor   39
    2.8  Register View of a System's Operation     43
    2.9  Summary                                   46
    2.10  Problems                                 47
  CHAPTER 3  Register View of 80C188EB Systems     51
    3.1  80C188EB CPU Subsystem                    52
    3.2  Memory Subsystem                          55
    3.3  I/O Subsystems                            57
    3.4  80C188EB Modular Core CPU                 59
    3.5  Memory Segmentation and the BIU's         62
    Segment Registers
    3.6  The EU and its Registers                  70
    3.7  Programmer's Register View of an          71
    80C188EB System
    3.8  The 80C186EB Microprocessor               72
    3.9  Summary                                   72
    3.10  Problems                                 73
  CHAPTER 4  Assembly Language and Assemblers      77
    4.1  Machine Language Instructions             78
    4.2  Assembly Language Instructions            80
    4.3  Simple Programs Structured as             84
    Sequential Tasks
    4.4  ASM86 Assembly Language and Assemblers    88
    4.5  Relocatable Program Modules and           91
    Location
    4.6  Embedded Assemblers Versus DOS            93
    Assemblers
    4.7  Intel's ASM86 Assembler and Utilities     94
    4.8  Assembly Language Programs that Run       100
    Under DOS
    4.9  Borland's TASM Assembler and              102
    Paradigm's LOCATE
    4.10  ROMable DOS and DOS Emulators            106
    4.11  Summary                                  107
    4.12  Problems                                 108
  CHAPTER 5  Debugging Tools                       111
    5.1  Debugger Fundamentals                     112
    5.2  Debugging Tools Overview                  116
    5.3  Borland's Turbo Debugger                  124
    5.4  Intel's RISM (Remote) Monitor             129
    5.5  PromICE ROM Emulator                      129
    5.6  Paradigm DEBUG/RT Remote Debugger         130
    5.7  CodeTAP Target Access Probe               133
    5.8  Intel EV80C186EB Evaluation Board         135
    5.9  Observing Instruction and Program         136
    Execution
    5.10  Summary                                  139
    5.11 Problems                                  140
  CHAPTER 6  Data Transfer, Data Allocation,       141
  and Addressing Modes
    6.1  Data Transfer and Addressing Modes        142
    6.2  I/O Port Addressing                       145
    6.3  Register Addressing                       148
    6.4  Immediate Addressing                      148
    6.5  Allocating RAM for Data Variables         150
    6.6  Memory Addressing Modes                   157
    6.7  Structures                                164
    6.8  Addressability and Segment Overrides      167
    6.9  Allocating ROM for Data Constants         167
    6.10  Address Object Transfers                 170
    6.11  80C186EB Data Transfer Considerations    172
    6.12  Summary                                  173
    6.13  Problems                                 173
  CHAPTER 7  Bit Manipulation, Branching, and      179
  Looping
    7.1  Flags Register                            180
    7.2  Logical Instructions                      182
    7.3  Shifts and Rotates                        185
    7.4  Unconditional Jumps                       188
    7.5  Conditional Jumps                         194
    7.6  Looping and Iteration Control             199
    7.7  Conditional Task Execution                202
    7.8  Repeated String Instructions              206
    7.9  Records                                   209
    7.10  Summary                                  211
    7.11  Problems                                 212
  CHAPTER 8  The Stack, Procedures, and Modular    217
  Software
    8.1  The Stack                                 218
    8.2  80C188EB Stack Allocation and Operation   220
    8.3  Procedures                                224
    8.4  Procedures in a Single Module Program     232
    8.5  Parameter Passing                         234
    8.6  Modular Software Design Using             244
    Procedures
    8.7  Procedure Sequencing Using a Finite       247
    State Machine
    8.8  Testing and Debugging Procedures          252
    8.9  Summary                                   253
    8.10  Problems                                 253
  CHAPTER 9  Arithmetic Operands and Arithmetic    257
    9.1  Numeric Operand Representations           258
    9.2  Unsigned Binary Arithmetic                259
    9.3  Signed Binary Arithmetic                  264
    9.4  Unpacked BCD Arithmetic                   269
    9.5  Packed BCD Arithmetic                     272
    9.6  Binary/BCD Conversions                    273
    9.7  Summary                                   273
    9.8  Problems                                  276
  CHAPTER 10  80C188EB CPU Subsystems              281
    10.1  CPU Subsystems                           282
    10.2  The 80C188EB Microprocessor              285
    10.3  System Clock, Reset, and Bus Cycles      287
    10.4  Address/Data Bus Demultiplexing          296
    10.5  A Fully Buffered 80C188EB CPU            299
    Subsystem
    10.6 Logic Family Compatibility, Loading,      302
    and Buffering
    10.7  A Minimum Component Complete System      309
    10.8  Single and Multi-Board Systems           311
    10.9  Peripheral Control Block (PCB)           315
    10.10  The 80C186EB Microprocessor             319
    10.11  Summary                                 320
    10.12  Problems                                321
  CHAPTER 11  Memory Subsystems                    325
    11.1  Memory Subsystems                        326
    11.2  Logical Structure and Operation of       328
    Memory ICs
    11.3  Static Random Access Memory, SRAM        333
    11.4  Erasable Programmable Read Only          337
    Memory
    11.5  Flash Memory                             339
    11.6  Memory Subsystem Design                  349
    11.7  80C188EB Memory Subsystem Design         351
    11.8  80C186EB Memory Subsystem Design         353
    11.9  Memory Address Decoding                  356
    11.10  The 80C188EB's Chip-Select Unit         358
    11.11  SSI and MSI External Address Decoders   364
    11.12  PLD External Address Decoders           366
    11.13  Summary                                 374
    11.14  Problems                                374
  CHAPTER 12  Basic I/O Subsystems                 377
    12.1  Basic I/O Ports                          378
    12.2  MSI I/O Ports                            384
    12.3  I/O Ports on Microprocessor              387
    Compatible ICs and Device Controllers
    12.4  I/O Port Address Decoding                388
    12.5  PLD External I/O Address Decoders        392
    12.6  SSI and MSI External I/O Address         394
    Decoders
    12.7  Conditional I/O                          397
    12.8  The 80C188EB Input/Output Unit           401
    12.9  Interfacing I/O Ports to an 80C186EB     408
    12.10  82C55A Programmable LSI I/O Ports       409
    12.11  Summary                                 415
    12.12  Problems                                416
  CHAPTER 13  Timing                               419
    13.1  Timing Constraints and System            420
    Architecture
    13.2  Instruction Execution Time               420
    13.3  Wait States                              423
    13.4  Memory IC Timing Parameters              425
    13.5  Memory Subsystem Timing Compatibility    429
    Calculations
    13.6  I/O Timing Considerations                441
    13.7  80C188EB Timer/Counter Unit              442
    13.8  82C54 Programmable Interval              453
    Timer/Counter
    13.9  Real-Time Clocks                         456
    13.10  Watchdog Timers                         459
    13.11  Summary                                 459
    13.12  Problems                                460
  CHAPTER 14  Interrupts and Exceptions            463
    14.1  Fundamental Interrupt Concepts           464
    14.2  80C188EB Interrupts and Interrupt        467
    Processing Sequence
    14.3  Interrupt Vector Table                   470
    14.4  80C188EB Hardware Interrupts             473
    14.5  80C188EB Interrupt Control Unit          480
    14.6 Interrupt Service Routines                491
    14.7  Interrupt Driven Systems                 496
    14.8  Software Interrupts and Exceptions       497
    14.9  Interrupt Priority and Latency           500
    14.10  82C59A Priority Interrupt Controller    503
    14.11  Debugging Hardware Interrupts           506
    14.12  Summary                                 507
    14.13  Problems                                508
  CHAPTER 15 Data Entry and Display                511
    15.1  User Data Entry                          512
    15.2  Mechanical Switches                      512
    15.3  Keypads and Keyboards                    525
    15.4  Optical Shaft Encoders                   532
    15.5  Displays                                 540
    15.6  LED Displays                             541
    15.7  Multiplexed Eight-Digit LED Display      547
    Driver
    15.8  Liquid Crystal Display (LCD) Modules     549
    15.9  Vacuum Fluorescent Display (VFD)         562
    Modules
    15.10  Summary                                 563
    15.11  Problems                                563
  CHAPTER 16  Serial I/O Subsystems                567
    16.1  Serial Data Transfer                     568
    16.2  Universal Asynchronous                   573
    Receiver/Transmitters
    16.3  The 80C188EB's Serial Communications     576
    Unit, SCU
    16.4  SCU Asynchronous Serial Transfers        577
    16.5  Circular Memory Buffers                  585
    16.6  RS-232 and Other Serial                  586
    Communications Interfaces
    16.7  Flow Control                             592
    16.8  "PC Type" UARTs                          594
    16.9  SCU Asynchronous Serial Transfer for     598
    Multiprocessor Systems
    16.10  Synchronous Serial Data Transfer        601
    16.11 Clocked Synchronous Transfers Using      602
    the SCU
    16.12  Summary                                 603
    16.13  Problems                                604
  CHAPTER 17  Analog Data and Analog Output        607
  Subsystems
    17.1  Analog Data and Analog I/O Subsystems    608
    17.2  Digital-to-Analog Converters (DACs)      610
    17.3  DAC to System Bus Interface              618
    17.4  Basic DAC Circuits                       624
    17.5  Loading and Impedance Considerations     627
    17.6  Operational Amplifiers                   630
    17.7  Analog Demultiplexers                    633
    17.8  Track-Holds                              636
    17.9  Digital Potentiometers                   640
    17.10  Summary                                 642
    17.11  Problems                                643
  CHAPTER 18  Analog Input Subsystems              647
    18.1  Analog Data Acquisition                  648
    18.2  Input Transducers                        649
    18.3  Analog Input Signal Conditioning         651
    18.4  Track-holds for Analog to Digital        657
    Conversion
    18.5  Analog-to-Digital Converters (ADCs)      658
    18.6  Direct Conversion Techniques             662
    18.7  Indirect Conversion Techniques           668
    18.8  Analog Multiplexers                      672
    18.9  Multichannel Data Acquisition System     675
    18.10  Summary                                 677
    18.11  Problems                                678
  CHAPTER 19  High Data Rate I/O                   681
    19.1  Programmed I/O and Interrupt Driven      682
    I/O Data Transfer Rates
    19.2  Hardware FIFO Buffers                    684
    19.3  DMA Transfers                            689
    19.4  The 80C188EB's Support for DMA and       692
    Multiple Bus Masters
    19.5  82C37A DMA Controller                    693
    19.6  80C18xEx Family Members with On-Chip     695
    DMA
    19.7  Summary                                  703
    19.8  Problems                                 704
  CHAPTER 20  Multi-Module and Multi-Language      705
  Programs
    20.1  Multi-Module Programs                    706
    20.2  Linking Multiple Modules                 709
    20.3  Managing Multi-module Programs with a    713
    Make Utility
    20.4  Segment Groups                           717
    20.5  Mixed Language Programs                  719
    20.6  Memory Models                            721
    20.7  Interfacing C and Assembly Language      722
    Modules
    20.8  Simplified Segment Directives            732
    20.9  Startup Code                             734
    20.10  Summary                                 735
Appendix A:  ASCII Codes                           739
Appendix B:  Some Useful URLs                      741
Appendix C:  Instruction Set Descriptions          743
Appendix D:  Instruction Set Opcodes and Clock     791
Cycles
Bibliography                                       801
Index                                              809