Low Power CMOS Design

• Low-voltage/low-power digital design
• Low-power memory and microprocessors
• Variable voltage and DC/DC converter circuits
• Power estimation and optimization tools
• Future technology and circuit trends

Low-Power CMOS Design is of special interest to portable system designers, digital and analog circuit and system designers, microprocessor designers, RF circuit ,and system designers, and CAD tool developers. It also provides an excellent background for mew. researchers, and can serve as a comprehensive textbook for graduate level courses.

Contents

Preface
Part I  Overview                                   1
  1.1  Low Power Microelectronics: Retrospect      3
  and Prospect
        J. Meindl (Proceedings of the IEEE,
        April 1995).
  1.2  Micropower IC                               20
        E. Vittoz (Proceedings of the IEEE
        European Solid State Circuits
        Conference, Grenoble, September 1980).
  1.3  Low-Power CMOS Digital Design               36
        A.P. Chandrakasan
        S. Sheng
        R.W. Brodersen (IEEE Journal of Solid
        State Circuits, April 1992).
  1.4  CMOS Scaling for High Performance and       47
  Low-Power-The Next Ten Years
        B. Davari
        R. Dennard
        G. Shahidi (Proceedings of the IEEE,
        April 1995).
Part II  Low Voltage Technologies and Circuits     59
  2.1  Low-Voltage Technologies and Circuits       61
        T. Kuroda
        T. Sakurai (INVITED PAPER).
SECTION 2.1  Threshold Voltage Scaling and         66
Control
  2.2  Ion-Implanted Complementary MOS             66
  Transistors in Low-Voltage Circuits
        R.M. Swanson
        J.D. Meindl (IEEE Journal of
        Solid-State Circuits, April 1972).
  2.3  Trading Speed for Low Power by Choice of    74
  Supply and Threshold Voltages
        D. Liu
        C. Svensson (IEEE Journal of
        Solid-State Circuits, January 1993).
  2.4 Limitation of CMOS Supply-Voltage Scaling    82
  by MOSFET Threshold-Voltage Variation
        S. Sun
        P. Tsui (IEEE Custom Integrated
        Circuits Conference, May 1994).
SECTION 2.2  Multiple Threshold CMOS (MTCMOS)      86
  2.5  1-V Power Supply High-Speed Digital         86
  Circuit Technology with Multithreshold
  Voltage CMOS
        S. Mutoh
        T. Douskei
        Y. Matsuya
        T. Aoki
        S. Shigematsu
        J. Yamada (IEEE Journal of Solid-State
        Circuits, August 1995).
  2.6  A 1-V Multi-Threshold Voltage CMOS DSP      93
  with an Efficient Power Management Technique
  for Mobile Phone Application
        S. Mutoh
        S. Shigematsu
        Y. Matsuya
        H. Fukuda
        J. Yamada (IEEE International
        Solid-State Circuits Conference,
        February 1996).
SECTION 2.3  Substrate Bias Controlled Variable    95
Threshold CMOS
  2.7  50% Active-Power Saving Without Speed       95
  Degradation Using Standby Power Reduction
  (SPR) Circuit
        K. Seta
        H. Hara
        T. Kuroda
        M. Kakumu
        T. Sakurai (IEEE International
        Solid-State Circuits Conference,
        February 1995).
  2.8  A 0.9V, 150MHz 10mW 4mm(2), 2-D Discrete    97
  Cosine Transform Core Processor with Variable
  Threshold-Voltage (VT) Scheme
        T. Kuroda
        T. Fujita
        S. Mita
        T. Nagamatsu
        S. Yoshioka
        K. Suzuki
        F. Sano
        M. Norishima
        M. Murota
        M. Kako
        M. Kinugawa
        M. Kakumu
        T. Sakurai (IEEE Journal of Solid-State
        Circuits, November 1996).
SECTION 2.4  Silicon-on-Insulator Based            105
Technologies
  2.9  SOI CMOS for Low Power Systems              105
        D. Antoniadis (INVITED PAPER).
  2.10  Back Gated CMOS on SOIAS for Dynamic       111
  Threshold Voltage Control
        I. Yang
        C. Vieri
        A.P. Chandrakasan
        D. Antoniadis (IEEE International
        Electron Devices Meeting (IEDM),
        December 1995).
  2.11  Design of Low Power CMOS/SOI Devices       115
  and Circuits for Memory and Signal Processing
  Applications
        L. Thon
        G. Shahidi (INVITED PAPER).
  2.12  A Dynamic Threshold Voltage MOSFET         121
  (DTMOS) for Very Low Voltage Operation
        F. Assaderaghi
        S. Parke
        D. Sinitsky
        J. Bokor
        P.K. Ko
        C. Hu (IEEE Electron Device Letters,
        December 1994).
  2.13  A 0.5V SIMOX-MTCMOS Circuit with 200ps     124
  Logic Gate
        T. Douseki
        S. Shigematsu
        Y. Tanabe
        M. Harada
        H. Inokawa
        T. Tsuchiya (IEEE International
        Solid-State Circuits Conference,
        February 1996).
Part III  Efficient DC-DC Conversion and           127
Adaptive Power Supply Systems
SECTION 3.1 Efficient Low Voltage DC-DC            129
Converter Design
  3.1  A Low-Voltage CMOS DC-DC Converter for a    129
  Portable Battery-Operated System
        A. Stratakos
        S. Sanders
        R. Brodersen (IEEE Power Electronics
        Specialists Conference, 1994).
  3.2  Ultra Low-Power Control Circuits for PWM    137
  Converters
        A. Dancy
        A. Chandrakasan (CONTRIBUTED PAPER).
SECTION 3.2  Adaptive Power Supply Systems         143
  3.3  A Voltage Reduction Technique for           143
  Battery Operated Systems
        V. von Kaenel
        P. Macken
        M. Degrauwe (IEEE Journal of
        Solid-State Circuits, October 1990).
  3.4  Automatic Adjustment of Threshold and       148
  Supply Voltage for Minimum Power Consumption
  in CMOS Digital Circuits
        V. von Kaenel
        M. Pardoen
        E. Dijkstra
        E. Vittoz (IEEE Symposium on Low-Power
        Electronics, October 1994).
  3.5  Low-Power Operation Using Self-Timed        150
  Circuits and Adaptive Scaling of the Supply
  Voltage
        L. Nielsen
        C. Niessen
        J. Sparso
        K. van Berkel (IEEE Transactions on
        VLSI Systems, December 1994).
  3.6  A Low-Power Switching Power Supply for      157
  Self-Clocked Systems
        G. Wei
        M. Horowitz (INVITED PAPER).
  3.7 Variable-Voltage Digital-Signal Processing   166
        V. Gutnik
        A. Chandrakasan (CONTRIBUTED PAPER).
  3.8  Scheduling for Reduced CPU Energy           177
        M. Weiser
        B. Welch
        A. Demers
        S. Shenker (First Symposium on
        Operating Systems Design and
        Implementation (OSDI), Usenix
        Association, 1994).
Part IV  Circuit and Logic Styles                  189
SECTION 4.1  Conventional Circuit and Logic        191
Styles
  4.1  Silicon-Gate CMOS Frequency Divider for     191
  the Electronic Wrist Watch
        E. Vittoz
        B. Gerber
        F. Leuenberger (IEEE Journal of
        Solid-State Circuits, April 1972).
  4.2  CODYMOS Frequency Dividers Achieve Low      196
  Power Consumption and High Frequency
        H. Oguey
        E. Vittoz (Electronics Letters, July
        1973).
  4.3  Short-Circuit Dissipation of Static CMOS    198
  Circuitry and Its Impact on the Design of
  Buffer Circuits
        H.J.M. Veendrick (IEEE Journal of
        Solid-State Circuits, August 1984).
  4.4  A 3.8ns CMOS 16 X 16 Multiplier Using       204
  Complementary Pass Transistor Logic
        K. Yano
        T. Yamanaka
        T. Nishida
        M. Saitoh
        K. Shimohigashi
        A. Shimizu. (IEEE Custom Integrated
        Circuits Conference, 1989).
  4.5  A High-Speed, Low-Power, Swing Restored     208
  Pass-Transistor Logic Based Multiply and
  Accumulate Circuit for Multimedia Applications
        A. Parameswar
        H. Hara
        T. Sakurai (Proceedings of Custom
        Integrated Circuits Conference, May
        1994).
  4.6  Static Power Driven Voltage Scaling and     212
  Delay Driven Buffer Sizing in Mixed Swing
  QuadRail for Sub-IV I/O Swings
        R. Krishnamurthy
        I. Lys
        L.R. Carley (International Symposium on
        Low-Power Electronics and Design,
        August 1996).
  4.7  The Power Consumption of CMOS Adders and    218
  Multipliers
        T. Callaway
        E. Swartzlander, Jr. (INVITED PAPER).
  4.8  Delay Balanced Multipliers for Low          225
  Power/Low Voltage DSP Core
        T. Sakuta
        W. Lee
        P.T. Balsara (IEEE Symposium on
        Low-Power Electronics: Digest of
        Technical Papers, October 1995).
  4.9  Asynchronous Does Not Imply Low Power,      227
  But
        K. Van Berkel
        H. van Gageldonk
        J. Kessels
        C. Niessen
        A. Peeters
        M. Roncken
        R. van de Wiel (INVITED PAPER).
  4.10  Latches and Flip-Flops for Low-Power       233
  Systems
        C. Svensson
        J. Yuan (INVITED PAPER).
SECTION 4.2  Adiabatic Logic Circuits              239
  4.11  Zig-Zag Path to Understanding              239
        R. Landauer (IEEE PhysComp '94).
  4.12  A Low-Power Multiphase Circuit Technique   245
        B. Watkins (IEEE Journal of Solid-State
        Circuits, December 1967).
  4.13  Asymptotically Zero Energy Split-Level     253
  Charge Recovery Logic
        S. Younis
        T. Knight (International Workshop on
        Low Power Design, 1994).
  4.14  Low Power Digital Systems Based on         259
  Adiabatic Switching Principles
        W.C. Athas
        L. Sevensson
        J.G. Koller
        N. Tzartzanis
        E.Y. Chou (IEEE Trans. on VLSI Systems,
        December 1994).
  4.15  Adiabatic Dynamic Logic                    268
        A. Dickinson
        J. Denker (IEEE Journal of Solid-State
        Circuits, March 1995).
Part V  Driving Interconnect                       273
  5.1  Sub-1-V Swing Internal Bus Architecture     275
  for Future Low-Power ULSIs
        Y. Nakagome
        K. Itoh
        M. Isoda
        K. Takeuchi
        M. Aoki (IEEE Journal of Solid-State
        Circuits, April 1993).
  5.2 Data-Dependent Logic Swing Internal Bus      281
  Architecture for Ultra Low-Power LSIs
        M. Hiraki
        H. Kojima
        H. Misawa
        T. Akazawa
        Y. Hatano (IEEE Journal of Solid-State
        Circuits, April 1995).
  5.3  An Asymptotically Zero Power                287
  Charge-Recycling Bus Architecture for
  Battery-Operated Ultra-High Data Rate ULSIs
        H. Yamauchi
        H. Akamatsu
        T. Fujita (IEEE Journal of Solid-State
        Circuits, April 1995).
  5.4  Bus-Invert Coding for Low Power I/O         296
        M. Stan
        W. Burleson (IEEE Trans. on VLSI
        Systems, March 1995).
  5.5  A Sub-CV(2) Pad Driver with 10 ns           306
  Transition Time
        L.J. Svensson
        W.C. Athas
        R.S-C. Wen (IEEE International
        Symposium on Low-Power Electronics and
        Design, August 1996).
Part VI  Memory Circuits                           311
  6.1  Reviews and Prospects of Low-Power          313
  Memory Circuits
        K. Itoh (INVITED PAPER).
SECTION 6.1  DRAM                                  318
  6.2  Trends in Low-Power RAM Circuit             318
  Technologies
        K. Itoh
        K. Sasaki
        Y. Nakagome (Proceedings of the IEEE,
        April 1995).
  6.3  Standby/Active Mode Logic for Sub-1V        338
  Operating ULSI Memory
        D. Takashima
        S. Watanabe
        H. Nakano
        Y. Oowaki
        K. Ohuchi
        H. Tango (IEEE Journal of Solid-State
        Circuits, April 1994).
  6.4  A Charge Recycle Refresh for Gb-scale       344
  DRAM's in File Application
        T. Kawahara
        Y. Kawajiri
        M. Horiguchi
        T. Akiba
        G. Kitsukawa
        T. Kure
        M. Aoki (IEEE Journal of Solid-State
        Circuits, June 1994).
SECTION 6.2 SRAM                                   352
  6.5  A 1-V 1-Mb SRAM for Portable Equipment      352
        H. Morimura
        N. Shibata (International Symposium on
        Low-Power Electronics and Design,
        August 1996).
  6.6  A Single Bitline Cross-Point Cell           358
  Activation (SCPA) Architecture for
  Ultra-Low-Power SRAMs
        M. Ukita
        S. Murakami
        T. Yamagata
        H. Kuriyama
        Y. Nishimura
        K. Anami (IEEE International
        Solid-State Circuits Conference,
        February 1994).
  6.7  Techniques to Reduce Power in Fast Wide     360
  Memories
        B. Amrutur
        M. Horowitz (Proceedings of the IEEE
        Symposium on Low Power Electronics,
        1994).
  6.8  A 2-ns, 5-mW, Synchronous-Powered           362
  Static-Circuit Fully Associative TLB
        H. Higuchi
        S. Tachibana
        M. Minami
        T. Nagano (IEEE Symposium on VLSI
        Circuits, June 1995).
  6.9  Driving Source-Line (DSL) Cell              364
  Architecture for Sub-1-V High Speed Low Power
  Applications
        H. Mizuno
        T. Nagano (IEEE Symposium of VLSI
        Circuits, June 1995).
Part VII  Portable Terminal Electronics            367
SECTION 7.1  General Purpose Processor Design      369
  7.1  Energy Dissipation in General Purpose       369
  Microprocessors
        R. Gonzalez
        M. Horowitz (IEEE Journal of
        Solid-State Circuits, September 1996).
  7.2  Energy Efficient CMOS Microprocessor        376
  Design
        T. Burd
        R. Brodersen (Proceedings of the 28th
        Annual HICSS Conference, January 1995).
  7.3  A 160MHz 32b 0.5W CMOS RISC                 386
  Microprocessor
        J. Montanaro
        R. Witek
        K. Anne
        A. Black
        E. Cooper
        D. Dobberpuhl
        P. Donahue
        J. Eno
        G. Hoeppner
        D. Kruckemyer
        T. Lee
        P. Lin
        L. Madden
        D. Murray
        M. Pearce
        S. Santhanam
        K. Snyder
        R. Stephany
        S. Thierauf (IEEE Journal of
        Solid-State Circuits, November 1996).
  7.4  A 320Mhz, 1.5mW @ 1.35V CMOS PLL for        396
  Microprocessor Clock Generation
        V. Von Kaenel
        D. Aebischer
        C. Piguet
        E. Dijkstra (IEEE Journal of
        Solid-State Circuits, November 1996).
SECTION 7.2  Dedicated and Programmable Digital    404
Signal Processors
  7.5  A Low-Power Chipset for a Portable          404
  Multimedia I/O Terminal
        A.P. Chandrakasan
        A. Burstein
        R.W. Brodersen (IEEE Journal of
        Solid-State Circuits, December 1994).
  7.6  A Portable Real-Time Video Decoder for      418
  Wireless Communication
        T. Meng
        B. Gordon
        E. Tsern (INVITED PAPER).
  7.7  Low Power Design of Memory Intensive        433
  Functions
        D. Lidsky
        J. Rabaey (IEEE Symposium on Low-Power
        Electronics, 1994).
  7.8  A 16b Low-Power Digital Signal Processor    435
        K. Ueda
        T. Sugimura
        M. Okamoto
        S. Marui
        T. Ishikawa
        M. Sakakihara (IEEE International
        Solid-State Circuits Conference,
        February 1993).
  7.9  A 1.8V 36mW DSP for the Half-Rate Speech    437
  CODEC
        T. Shiraishi
        K. Kawamoto
        K. Ishikawa
        H. Sato
        F. Asai
        E. Teraoka
        T. Kengaku
        H. Takata
        T. Tokuda
        K. Nishida
        K. Saitoh (Proceedings of the IEEE
        Custom Integrated Circuits Conference,
        May 1996).
  7.10  Design of a 1-V Programmable DSP for       441
  Wireless Communication
        P. Landman
        W. Lee, B. Barton
        S. Abiko
        H. Takahashi
        H. Mizuno. S. Muramatsu
        K. Tashiro
        M. Fusumada
        L. Pham
        F. Boutaud
        E. Ego
        G. Gallo
        H. Tran
        C. Lemonds
        A. Shih
        M. Nandakumar
        B. Eklund
        I-C. Chen (INVITED PAPER).
  7.11  Stage-Skip Pipeline: A Low Power           450
  Processor Architecture Using a Decoded
  Instruction Buffer
        M. Hiraki
        R. Bajwa
        H. Kojima
        D. Gorny
        K. Nitta
        A. Shridhar
        K. Sasaki
        K. Seki (International Symposium on Low
        Power Electronics and Design, August
        1996).
Part VIII  Computer Aided Design Tools             457
SECTION 8.1  Power Analysis Techniques             459
  8.1  Transition Density: A New Measure of        459
  Activity in Digital Circuits
        F. Najm (IEEE Trans. on Computer Aided
        Design of Integrated Circuits and
        Systems, February 1993).
  8.2  Estimation of Average Switching Activity    473
  in Combinational and Sequential Circuits
        A. Ghosh
        S. Devadas
        K. Keutzer
        J. White (IEEE/ACM Design Automation
        Conference, June 1992).
  8.3  Power Estimation for Sequential Logic       480
  Circuits
        C. Tsui
        J. Monteiro
        M. Pedram
        S. Devadas
        A. Despain
        B. Lin (IEEE Trans. on VLSI Systems,
        September 1995).
  8.4  A Monte Carlo Approach for Power            492
  Estimation
        R. Burch
        F.N. Najm
        P. Yang
        T. Trick (IEEE Transactions on VLSI
        Systems, March 1993).
  8.5  Stratified Random Sampling for Power        501
  Estimation
        C.-S. Ding
        C.-T. Hsieh
        Q. Wu
        M. Pedram (IEEE/ACM International
        Conference on Computer-Aided Design,
        November 1996).
  8.6  A Survey of High-Level Power Estimation     508
  Techniques
        P. Landman (INVITED PAPER).
  8.7  Activity-Sensitive Architectural Power      516
  Analysis
        P. Landman
        J. Rabaey (IEEE Transactions on CAD,
        June 1996).
  8.8  Power Analysis of Embedded Software: A      533
  First Step Towards Software Power Minimization
        V. Tiwari
        S. Malik
        A. Wolfe (IEEE Trans. on VLSI Systems,
        December 1994).
SECTION 8.2  Power Optimization Techniques         542
  8.9  Technology Mapping for Low Power            542
        V. Tiwari
        P. Ashar
        S. Malik (Proceedings of the IEEE/ACM
        30th Design Automation Conference, June
        1993).
  8.10  POSE: Power Optimization and Synthesis     548
  Environment
        S. Iman
        M. Pedram (IEEE/ACM 33rd Design
        Automation Conference, June 1996).
  8.11  Transformation and Synthesis of FSMs       554
  for Low-Power Gated-Clock Implementation
        L. Benini
        G. De Micheli (International Symposium
        of Low Power Design, April 1995).
  8.12  Precomputation-Based Sequential Logic      560
  Optimization for Low Power
        M. Alidina
        J. Monteiro
        S. Devadas
        A. Ghosh
        M. Papaefthymiou (Proceedings of the
        IEEE/ACM International Conference on
        Computer-Aided Design, November 1994).
  8.13  Glitch Analysis and Reduction in           568
  Register Transfer Level Power Optimization
        A. Raghunathan
        S. Dey
        N. Jha (IEEE/ACM 33rd Design Automation
        Conference, June 1996).
  8.14  Exploiting Locality for Low-Power Design   574
        R. Mehra
        L. Guerra
        J. Rabaey (Proceedings of the IEEE
        Custom Integrated Circuit Conference,
        May 1996).
  8.15  HYPER-LP: A System for Power               578
  Minimization Using Architectural
  Transformations
        A.P. Chandrakasan
        M. Potkonjak
        J. Rabaey
        R.W. Brodersen (IEEE/ACM International
        Conference on Computer-Aided Design,
        November 1992).
  8.16  Variable Voltage Scheduling                582
        S. Raje
        M. Sarrafzadeh (International Symposium
        on Low Power Design, April 1995).
  8.17  System-Level Transformations for Low       609
  Power Data Transfer and Storage
        F. Catthoor
        S. Wuytack
        E. de Greef
        F. Franssen
        L. Nachtergaele
        H. Deman (INVITED PAPER).
Author Index                                       619
Index                                              623