PowerPC Microprocessor Common Hardware Reference Platform

This book is the primary source of information for anyone developing a hardware platform, an operating system, or hardware component to be part of these standard systems. It describes the hardware to operating system interface that is essential to anyone building hardware platforms and provides the minimum system configurations platform designers must meet when building a standard platform. Component manufacturers require this information to produce compatible chips and adapters to use on these platforms, and software developers require the information on mandatory functions and documented interfaces.

The architecture is intended to support a range of PowerPC microprocessor based system implementations including portable, desktop, and server class systems, and allows multiple operating system implementations across a wide range of environments and functions. This enables new hardware and software enhancements which are necessary for the development of improved user interfaces, higher performance, and broader operating environments.

Table of contents

Foreword vii
List of Figures xiii
List of Tables xv
About this Document xvii
Goals of the Specification xviii
Audience for this Document xix
Organization of this Document xx
Suggested Reading xxii
Conventions Used in this Document xxiii
Acknowledgments xxiv
Comments on this Document xxiv
Chapter 1 Introduction 1
1.1 Platform Topology 2
Chapter 2 System Requirements 7
2.1 System Operation 7
2.1.1 Control Flow 7
2.1.2 POST 8
2.1.3 Boot Phase 8
2.1.4 Transfer Phase 11
2.1.5 Run-Time 12
2.1.6 Termination 12
2.2 Firmware 13
2.3 Bi-Endian Support 14
2.4 64-Bit Addressing Support 14
2.5 Minimum System Requirements 16
2.5.1 Table Description 17
2.6 Options and Extensions 20
Chapter 3 System Address Map 23
3.1 Address Areas 23
3.2 Address Decoding and Translation 28
3.2.1 Peripheral 1/0 Address Translation 37
3.2.2 Translation of 32-Bit DMA Addresses in 64-Bit Addressing Systems 38
3.3 PC Emulation Option 44
Chapter 4 Processor and Memory 49
4.1 Processor Architecture 49
4.1.1 Processor Architecture Compliance 50
4.1.2 PowerPC Microprocessor Differences 51
4.1.3 Processor Interface Variations 53
4.1.4 PowerPC Architecture Features Deserving Comment 53
4.2 Memory Architecture 56
4.2.1 System Memory 56
4.2.2 Storage Ordering Models 57
4.2.3 Memory Controllers 64
4.2.4 Cache Memory 65
Chapter 5 I/0 Bridges 69
5.1 PCI Host Bridge (PHB) Architecture 69
5.1.1 PHB Implementation Options 70
5.1.2 Data Buffering and Instruction Queuing 70
5.1.3 Byte Ordering Conventions 74
5.1.4 PCI Bus Protocols 77
5.1.5 Programming Model 78
5.2 I/0 Bus to I/0 Bus Bridges 78
5.2.1 What Must Talk to What 79
5.2.2 PCI to PCI Bridges 81
5.2.3 PCI to ISA Bridges 82
5.2.4 16-Bit PC Card (PCMCIA) and Cardbus PC Card Bridges 83
Chapter 6 Interrupt Controller 85
6.1 Interrupt Controller Architecture 85
6.2 Distributed Implementation-A Proposal 86
Chapter 7 Run-Time Abstraction Services 91
7.1 RTAS Introduction 91
7.2 RTAS Environment 92
7.2.1 Machine State 93
7.2.2 Register Usage 94
7.2.3 RTAS Critical Regions 95
7.2.4 Resource Allocation and Use 96
7.2.5 Instantiating RTAS 97
7.2.6 RTAS Device Tree Properties 98
7.2.7 Calling Mechanism and Conventions 101
7.2.8 Return Codes 103
7.3 RTAS Call Function Definition 103
7.3.1 restart-rtas 104
7.3.2 NVRAM Access Functions 106
7.3.3 Time of Day 109
7.3.4 Error and Event Reporting 114
7.3.5 PCI Configuration Space 117
7.3.6 operator Interfaces and Platform Control 123
7.3.7 Power Management 128
7.3.8 Suspend and Hibernate 135
7.3.9 Reboot 136
7.3.10 Caches 137
7.3.11 SMP Support 141
Chapter 8 Non-Volatile Memory 141
8.1 System Requirements 142
8.2 Structure 142
8.3 Signatures 144
8.4 Architected Partitions 144
8.4.1 Open Firmware (5x50) 145
8.4.2 Hardware (0x52) 145
8.4.3 System (0x70) 145
8.4.4 Configuration (0x71) 147
8.4.5 Error Log (0x72) 147
8.4.6 Multi-Boot (0x73) 148
8.4.7 Free Specs (0x7F) 149
8.5 NVRAM Space Management 149
Chapter 9 I/0 Devices 151
9.1 PCI Devices 152
9.1.1 Resource Locking 152
9.1.2 PCI Expansion ROMS 152
9.1.3 Assignment of Interrupts to PCI Devices 153
9.1.4 PCI Devices with Required Register Definitions 154
9.1.5 PCI-PCI Bridge Devices 154
9.1.6 Graphics Controller and Monitor Requirements for Clients 155
9.2 ISA Devices 155
Chapter 10 Error and Event Notification 157
10.1 Introduction 158
10.2 RTAS Error and Event Classes 150
10.2.1 Internal Error Indications 165
10.2.2 Environmental and Power Warnings 167
10.2.3 Power Management Events 167
10.3 RTAS Error and Event Information Reporting 168
10.3.1 Introduction 168
10.3.2 RTAS Error/Event Return Format 168
Chapter 11 Power Management 185
11.1 Power Management Concepts 186
11.1.1 Power Management Policy Versus Mechanism 187
11.1.2 Device Power States 187
11.1.3 System Power Management States 187
11.1.4 System Power Transitory States 190
11.1.5 Power Domains and Domain Control Points 191
11.1.6 Power Sources 195
11.1.7 Batteries 195
11.1.8 Power Management Events 195
11.1.9 Explicit Transfer of Power Management Policy 196
11.1.10 EPA Energy Star Compliance 197
11.2 Power-Managed Platform Requirements 197
11.2.1 Definition of Power Management Related Parameters Utilized by RTAS 198
11.2.2 Open Firmware Device Tree Properties 201
11.2.3 General Hardware Requirements 205
11.3 Operating System Requirements 210
11.3.1 General Requirements 212
Chapter 12 The Symmetric Multiprocessor Option 215
12.1 SMP System Organization 216
12.2 An SMP Boot Process 218
12.2.1 SMP-Safe Boot 219
12.2.2 Finding the Processor Configuration 220
12.2.3 SMP-Efficient Boot 222
12.2.4 Use of a Service Processor 222
Appendix A Operating System Information 223
Appendix B Requirements Summary 225
Appendix C Bi-Endian Designs 265
C.1 Little-Endian Address and Data Translation 265
C.2 Conforming Bi-Endian Designs 268
C.2.1 Processor and I/0 Mode Control 268
C.2.2 Approach #1-Bi-Endian Memory and Si-Endian I/O Design 269
C.2.3 Approach #2-Bi-Endian I/O Design 273
C.3 Software Support for Bi-Endian Operation 276
C.4 Bi-Modal Devices 276
C.5 Future Directions In Bi-Endian Architecture 279
Appendix D Architecture Migration Notes 281
Glossary 285
Trademark Information 295
Bibliography 297
Sources for Documents 299
Obtaining Additional Information 300
Index 303