CMOS/BiCMOS ULSI

Low Voltage, Low Power

Kiat-Seng Yeo, Samir S. Rofail, Wang-Ling Goh

384 pages, parution le 16/01/2002

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Résumé

CMOS/BICMOS ULSI presents state-of-the-art BiCMOS low-voltage, low-power design techniques for ULSI and giga-scale integration engineering, covering process integration, device modeling, and characterization. Discover the latest MOS and bipolar models; breakthroughs in copper metallization, isolation, and deep submicron processes; and new approaches to designing logic gates, latches, and flip-flops.

Preface
Acknowledgements
Nomenclature
1: Introduction: Low-Power Design: An Overview; Low-Voltage Low-Power Design Limitations; Silicon-On-Insulator (SOI); From Devices to Circuits
2: MOS/BiCMOS Process Technology and Integration: The Realization of BiCMOS Processes; BiCMOS Manufacturing and Integration Considerations; Isolation in BiCMOS; Integrated Analog/Digital BiCMOS Process; Deep Submicron Processes; Low-Voltage/Low-Power CMOS/BiCMOS Processes; Future Trends and Directions of CMOS/BiCMOS Processes; Conclusions
3: Device Behavior and Modeling: The MOS(FET) Transistor; The Bipolar (Junction) Transistor; MOSFET SPICE Models; ADVANCE MOSFET Models; BIPOLAR SPICE Models; The MOSFET in a Hybrid Mode Environment; Summary; Appendix A; Appendix B; Appendix C; Appendix D
4: Low-Voltage Low-Power Logic Circuits: Conventional CMOS Logic Gates; Conventional BiCMOS Logic Gate; BiCMOS Circuits Utilizing Lateral pnp BJTs in pMOS Structures; Merged BiCMOS (MBiCMOS) Digital Circuits; Full-Swing Multi-Drain/Multi-Collector Complementary BiCMOS Buffers; Quasi-Complementary BiCMOS (QC-BiCMOS) Digital Circuits; Full-Swing BiCMOS/BiNMOS Digital Circuits Employing Schottky Diodes; Feedback-Type BiCMOS Digital Circuits; High-Beta BiCMOS (HB-BiCMOS) Digital Circuits; Transiently Saturated Full-Swing BiCMOS Digital Circuits; Bootstrapped-Type BiCMOS Digital Circuits; Electrostatic Discharge Free BiCMOS Digital Circuit; Conclusion
5: Low-Voltage Low-Power Latches and Flip-flops: Evolution of Latches and Flip-Flops; Quality Measures for Latches and Flip-Flops; Latches and Flip-Flops: A Design Perspective
The Authors
Index

L'auteur - Kiat-Seng Yeo

Kiat-Seng Yeo

joined the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore in 1993. He is now the Sub-Dean of EEE, Principal Investigator of NTU's Integrated Circuit Technology Research Group, Program Manager of the System-on-Chip Flagship Project, Coordinator of the Integrated Circuit Design Research Group, Technical Chairman of the 8th and 9th International Symposium on Integrated Circuits, Devices and Systems, and a Technical Consultant. He holds six patents and published more than 100 articles in BiCMOS/CMOS integrated circuit design and technology.

L'auteur - Samir S. Rofail

Samir S. Rofail

has been a teacher, researcher, and consultant in semiconductor and IC design for 20 years. From 1992 to 1999, he coordinated NTU's IC-Design group, leading intensive research on low-voltage, low-power BiCMOS/CMOS circuits. He is now a technical consultant in Waterloo, Canada.

L'auteur - Wang-Ling Goh

Wang-Ling Goh

joined NTU in 1996. Her research interests are in the areas of silicon processing technologies, particularly the SOI structures, CMP and Copper. She holds one patent and has published over 30 articles in the above named areas.

Caractéristiques techniques

	PAPIER
Éditeur(s)	Prentice Hall
Auteur(s)	Kiat-Seng Yeo, Samir S. Rofail, Wang-Ling Goh
Parution	16/01/2002
Nb. de pages	384
Format	18,5 x 24
Couverture	Broché
Poids	1093g
Intérieur	Noir et Blanc
EAN13	9780130321626