Comprehensive Functional Verification

The Complete Industry Cycle

Bruce Wile, John C. Goss, Wolfgang Roesner

704 pages, parution le 29/11/2005

Ajouter à une liste

Indisponible

Résumé

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.

As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.

A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.

L'auteur - Bruce Wile

Bruce Wile : IBM Corporation, Poughkeepsie, NY

L'auteur - John C. Goss

John Goss : IBM Corporation, Research Triangle Park, NC

L'auteur - Wolfgang Roesner

Wolfgang Roesner : IBM Corporation, Austin, TX

Sommaire

Introduction to Verification
- Verification in the Chip Design Process
- Verification Flow
- Fundamentals of Simulation Based Verification
- The Verification Plan
Simulation Based Verification
- HDLs and Simulation Engines
- Creating Environments
- Strategies for Simulation based Stimulus Generation
- Strategies for Results Checking in Simulation Based Verification
- Pervasive Function Verification
- Re-Use Strategies and System Simulation
Formal Verification
- Introduction to Formal Verification
- Using Formal Verification
Comprehensive Verification
- Completing the Verification Cycle
- Advanced Verification Techniques
Case Studies
- Case Studies

Voir tout

Replier

Caractéristiques techniques

	PAPIER
Éditeur(s)	Morgan Kaufmann, Elsevier
Auteur(s)	Bruce Wile, John C. Goss, Wolfgang Roesner
Parution	29/11/2005
Nb. de pages	704
Format	19 x 24
Couverture	Relié
Poids	1580g
Intérieur	Noir et Blanc
EAN13	9780127518039
ISBN13	978-0-12-751803-9