Digital Integrated Circuits

A Design Perspective

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic

784 pages, parution le 28/01/2003 (2^eme édition)

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Résumé

Since the publication of the first edition of this hook in 1996. CMOS manufacturing technology has continued its breathtaking pace, scaling to ever-smaller dimensions. Minimum feature sizes are now reaching the 100-nm realm. Circuits are becoming more complex, challenging the productivity of the designer, while the plunge into the deep-submicron space causes devices to behave differently and brings to the forefront a number of new issues that impact the reliability, cost, performance, power dissipation, and reliability of the digital 1C. This updated text reflects the ongoing (r)evolution in the world of digital integrated circuit design, caused by this move into the deep-submicron realm. This means increased importance of deep-submicron transistor effects, interconnect, signal integrity, high-performance and low-power design, liming, and clock distribution. In contrast to the first edition, the present text focuses entirely on CMOS ICs.

Even more than for the first edition, this book uses its companion website to evolve and grow over time. Its contains complete Microsoft PowerPoint Presentations covering all the material, updates, corrections, design projects, and extensive instructor material. Most importantly, all problem sets are now available on the website (and have been removed from the text).

Outstanding Features of the Text

It focuses solely on deep-submicron CMOS devices, the workhorses of today's digital integrated circuits. A simple transistor model for manual analysis, called the unified MOS model, has been developed and is used throughout.
Design Examples stress the design of Digital ICs from a real-world perspective. Design challenges and guidelines are highlighted. 0.25-micron CMOS technology is used for all the examples and problems.
Design Methodology inserts are interspersed throughout the text, highlighting the importance of methodology and tools in today's design process.
A Perspective section at the end of each chapter gives an insight into future evolutions.

Contents

The Fabrics

Introduction
The Manufacturing Process
Design Methodology Insert A - IC Layout
The Devices
Design Methodology Insert B - Circuit Simulation
The Wire

A Circuit Perspective

The CMOS Inverter
Designing Combinational Logic Gates in CMOS
Design Methodology Insert C - How to Simulate Complex
Design Methodology Insert D - Layout Techniques for Complex Gates
Designing Sequential Logic Circuits

A System Perspective

Implementation Strategies for Digital ICS
Design Methodology Insert E - Characterizing Logic and Sequential Cells
Design Methodology Insert F - Design Synthesis
Coping with Interconnect
Timing Issue in Digital Circuits
Design Methodology Insert G - Design Verification
Designing Arithmetic Building Blocks
Designing Memory and Array Structures
Design Methodology Insert H - Validation and Test of Manufactured Circuits

L'auteur - Anantha Chandrakasan

Anantha Chandrakasan is an assistant professor in the Electrical Engineering and Computer Science Department at Massachusetts Institute of Technology. From 1994 through 1997, he held the Analog Devices Career Development Chair, and has received several awards including the NSF Career Development Award in 1995, the IBM Faculty Development Award in 1995, and the National Semiconductor Faculty Development Award in 1996.

Caractéristiques techniques

	PAPIER
Éditeur(s)	Prentice Hall
Auteur(s)	Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic
Parution	28/01/2003
Édition	2^eme édition
Nb. de pages	784
Format	17,7 x 23,4
Couverture	Broché
Poids	1102g
Intérieur	Noir et Blanc
EAN13	9780131207646
ISBN13	978-0-13-120764-6