Nanoscale Memory Repair

Masashi Horiguchi, Kiyoo Itoh - Collection Integrated Circuits and Systems

218 pages, parution le 15/01/2011

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Résumé

Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. As a result, repair techniques have been indispensable for nano-scale memories. Without these techniques, even modern MPUs/ SoCs, in which memories have dominated the area and performance, could not have been designed successfully.

This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors' long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.

Presents the first comprehensive reference to reliability and repair techniques for nano-scale memories;
Covers both the mathematical foundations and engineering applications of yield and reliability in nano-scale memories;
Includes a variety of practical circuits and logic, critical for higher yield and reliability, which have been proven successful during the authors' extensive experience in developing memories and low-voltage CMOS circuits.

Sommaire

An Introduction to Repair Techniques
Redundancy
Error Checking and Correction (ECC)
Combination of Redundancy and Error Correction
Reduction Techniques for Margin Errors of Nanoscale Memories
Reduction Techniques for Speed-Relevant Errors of Nanoscale Memories
Index

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Caractéristiques techniques

	PAPIER
Éditeur(s)	Springer
Auteur(s)	Masashi Horiguchi, Kiyoo Itoh
Collection	Integrated Circuits and Systems
Parution	15/01/2011
Nb. de pages	218
Format	15 x 23,5
Couverture	Relié
Poids	300g
Intérieur	Noir et Blanc
EAN13	9781441979575
ISBN13	978-1-4419-7957-5