Testing of digital systems

Niraj Jha, Sandeep Gupta

1010 pages, parution le 19/05/2003

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Indisponible

Résumé

Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year.

The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis.

The book includes detailed treatment of the latest techniques including test generation for various fault modes, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis.

Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

Contents

Introduction
Fault models
Combinational logic and fault simulation
Test generation for combinational circuits
Sequential ATPG
IDDQ testing
Functional testing
Delay fault testing
CMOS testing
Fault diagnosis
Design for testability
Built-in self-test
Synthesis for testability
Memory testing
High-level test synthesis
System-on-a-chip testing

Index

Caractéristiques techniques

	PAPIER
Éditeur(s)	Cambridge University Press
Auteur(s)	Niraj Jha, Sandeep Gupta
Parution	19/05/2003
Nb. de pages	1010
Format	18 x 25,3
Couverture	Relié
Poids	2175g
Intérieur	Noir et Blanc
EAN13	9780521773560
ISBN13	978-0-521-77356-0