VHDL for Programmable Logic

Practical, clearly organized, up-to-date and user-friendly, Kevin Skahill's VHDL for Programmable Logic gives you the tools you need to learn how to program in VHDL and how to use VHDL to synthesize circuits -- including a complete professional VHDL software tool, Warp2 from Cypress Semiconductor

The VHDL Programmable Logic Instructor's Solutions Manual is now available in Adobe Acrobat format on our ftp site. Please contact your sales specialist for a password to allow access.

Whether you are a student looking for a dynamic, real-world introduction to an industry-standard HDL, or a professional engineer in need of a fast, effective approach to VHDL, VHDL for Programmable Logic will get you up to speed.

This hands-on tutorial explains the architecture, features, and technologies of programmable logic and teaches how to write VHDL code for synthesis. Many practical design examples focus on state machine design, counters, shifters, arithmetic circuits, control logic, FIFOs, and other "glue logic" that designers typically implement in programmable logic.

Included with the book is a CD-ROM containing Cypress Semiconductor's Warp2, a fully functional professional VHDL synthesis tool for Windows PCs and Sun workstations. Warp2 is a CPLD and FPGA synthesis, fitting, placement and routing software tool, which includes an interactive waveform simulator that performs functional simulation of CPLDs. Warp2 will allow the student or professional to use VHDL to design, simulate, and implement digital systems in programmable logic

Preface

Chapter 1: Introduction

1. Why Use VHDL?
2. Shortcomings
3. Using VHDL for Design Synthesis
4. Design Tool Flow
5. Our System
6. Font Conventions
7. Summary
8. Breakout Exercise 1.1
9. Problems

Chapter 2: Programmable Logic Primer

1. Introduction
2. Why Use Programmable Logic?
3. What Is a Programmable Logic Device?
4. Simple PLDs
5. What Is a CPLD?
6. What Is an FPGA?
7. PREP Benchmarks
8. Future Direction of Programmable Logic
9. Breakout Exercise 2.1
10. Breakout Exercise 2.2
11. Breakout Exercise 2.3
12. Breakout Exercise 2.4
13. Problems

Chapter 3: Entities and Architectures

1. Introduction
2. A Simple Design
3. Design Entities
4. Identifiers, Data Objects, Data Types, and Attributes
5. Common Errors
6. Breakout Exercise 3.1
7. Breakout Exercise 3.2
8. Breakout Exercise 3.3
9. Problems

Chapter 4: Creating Combinational and Synchronous Logic

1. Introduction
2. Design Example
3. Combinational Logic
4. Synchronous Logic
5. Designing a FIFO
6. Common Errors
7. Test Benches
8. Breakout Exercise 4.1
9. Breakout Exercise 4.2
10. Breakout Exercise 4.3
11. Problems

Chapter 5: State Machine Designs

1. Introduction
2. A Simple Design Example
3. A Memory Controller
4. Mealy State Machines
5. Additional Design Considerations
6. Summary
7. Breakout Exercise 5.1
8. Breakout Exercise 5.2
9. Problems

Chapter 6: Hierarchy in Large Designs

1. Introduction
2. Case Study: The AM2901
3. Case Study: A 100BASE--T4 Network Repeater
4. Breakout Exercise 6.1
5. Breakout Exercise 6.2
6. Problems

Chapter 7: Functions and Procedures

1. Introduction
2. Functions
3. Procedures
4. About Subprograms
5. Breakout Exercise 7.1
6. Problems

Chapter 8: Synthesis and Design Implementation

1. Introduction
2. Design Implementation: An Example
3. Synthesis and Fitting
4. CPLDs: A Case Study
5. FPGAs: A Case Study
6. Breakout Exercise 8.1
7. Breakout Exercise 8.2
8. Problems

Chapter 9: Optimizing Datapaths

1. Introduction
2. Pipelining
3. Resource Sharing
4. Magnitude Comparators
5. Fast Counters
6. Breakout Exercise 9.1
7. Problems

Chapter 10: Creating Test Benches

1. Introduction
2. Approaches to Writing Test Benches
3. Overloaded Read and Write Procedures
4. Breakout Exercise 10.1
5. Problems

Afterword
Review
Where To Go from Here

Appendix A: Viewing On-line Documentation and Installing Warp
Appendix B: Reserved Words
Appendix C: STD_logic_1164 Package
Appendix D: Quick Reference Guide
Glossary
Bibliography
Index