The Designer's Guide to VHDL

Table of contents

Foreword
Preface
1 Fundamental Concepts

1.1 Modeling Digital Systems
1.2 Domains and Levels of Modeling
1.3 Modeling Languages
1.4 VHDL Modeling Concepts

Elements of Behavior
Elements of Structure
Mixed Structural and Behavioral Models
Test Benches
Analysis, Elaboration and Execution

1.5 Learning a New Language: Lexical Elements and Syntax

Lexical Elements
Syntax Descriptions

Exercises

2.1 Constants and Variables

Constant and Variable Declarations
Variable Assignment

2.2 Scalar Types

Type Declarations
Integer Types
Floating-Point Types
Physical Types
Enumeration Types

2.3 Type Classification

Subtypes
Type Qualification
Type Conversion

2.4 Attributes of Scalar Types
2.5 Expressions and Operators
Exercises

3.1 If Statements
3.2 Case Statements
3.3 Null Statements
3.4 Loop Statements

Exit Statements
Next Statements
While Loops
For Loops
Summary of Loop Statements

3.5 Assertion and Report Statements
Exercises

4.1 Arrays

Multidimensional Arrays
Array Aggregates
Array Attributes

4.2 Unconstrained Array Types

Strings
Bit Vectors
Standard-Logic Arrays
String and Bit-String Literals
Unconstrained Array Ports

4.3 Array Operations and Referencing

Array Slices
Array Type Conversions

4.4 Records

Record Aggregates

Exercises

5.1 Entity Declarations
5.2 Architecture Bodies

Concurrent Statements
Signal Declarations

5.3 Behavioral Descriptions

Signal Assignment
Signal Attributes
Wait Statements
Delta Delays
Transport and Inertial Delay Mechanisms
Process Statements
Concurrent Signal Assignment Statements
Concurrent Assertion Statements
Entities and Passive Processes

5.4 Structural Descriptions

Component Instantiation and Port Maps

5.5 Design Processing

Analysis
Design Libraries, Library Clauses and Use Clauses
Elaboration
Execution

Exercises

6.1 Algorithm Outline

MAC Entity Declaration

6.2 A Behavioral Model

Testing the Behavioral Model

6.3 A Register-Transfer-Level Model

Modules in the Register-Transfer-Level Model
The Register-Transfer-Level Architecture Body
Testing the Register-Transfer-Level Model

Exercises

7.1 Procedures

Return Statement in a Procedure

7.2 Procedure Parameters

Signal Parameters
Default Values
Unconstrained Array Parameters
Summary of Procedure Parameters

7.3 Concurrent Procedure Call Statements
7.4Functions

Functional Modeling
Pure and Impure Functions
The Function Now

7.5 Overloading

Overloading Operator Symbols

7.6 Visibility of Declarations
Exercises

8.1 Package Declarations

Subprograms in Package Declarations
Constants in Package Declarations

8.2 Package Bodies
8.3 Use Clauses
8.4 The Predefined Package Standard
Exercises

9.1 Aliases for Data Objects
9.2 Aliases for Non-Data Items
Exercises

10.1 The Package Interface
10.2 The Package Body
10.3 An ALU Using the Arithmetic Package
Exercises

11.1 Basic Resolved Signals

Composite Resolved Subtypes
Summary of Resolved Subtypes

11.2 IEEE Std_Logic_1164 Resolved Subtypes
11.3 Resolved Signals and Ports

Resolved Ports
Driving Value Attribute

11.4 Resolved Signal Parameters
Exercises

12.1 Parameterizing Behavior
12.2 Parameterizing Structure
Exercises

13.1 Components

Component Declarations
Component Instantiation
Packaging Components

13.2 Configuring Component Instances

Basic Configutration Declarations
Configuring Multiple Levels of Hierarchy
Direct Instantiation of Configured Entities
Generic and Port Maps in Configurations
Deferred Component Binding

13.3 Configuration Specifications

Incremental Binding

Exercises

14.1 Generating Iterative Structures
14.2 Conditionally Generating Structures

Recursive Structures

14.3 Configuration of Generate Statements
Exercises

15.1 Overview of the DLX CPU

DLX Registers
DLX Instruction Set
DLX External Interface

15.2 A Behavioral Model

The DLX Types Package
The DLX Entity Declaration
The DLX Instruction Set Package
The DLX Behavioral Architecture Body

15.3 Testing the Behavioral Model

The Test-Bench Clock Generator
The Test-Bench Memory
The Test-Bench Architecture Body and Configuration

15.4 A Register-Transfer-Level Model

The Arithmetic and Logic Unit
The Registers
The Register File
The Multiplexer
The Extenders
The Architecture Body
The Controller
The Configuration Declaration

15.5 Testing the Register-Transfer-Level Model
Exercises

16.1 Guarded Signals and Disconnection

The Driving Attribute
Guarded Ports
Guarded Signal Parameters

16.2 Blocks and Guarded Signal Assignment

Explicit Guard Signals
Disconnection Specifications

16.3 Using Blocks for Structural Modularity

Generics and Ports in Blocks
Configuring Designs with Blocks

Exercises

17.1 Access Types

Access Type Declarations and Allocators
Assignment and Equality of Access Values
Access Types for Records and Arrays

17.2 Linked Data Structures

Deallocation and Storage Management

17.3 Abstract Data Types Using Packages

Container ADTs

Exercises

18.1 Files

File Declarations
Reading from Files
Writing to Files
Files Declared in Subprograms
Explicit Open and Close Operations
File Parameters in Subprograms
Portability of Files

18.2 The Package Textio

Textio Read Operations
Textio Write Operations
Reading and Writing User-Defined Types

Exercises

19.1 Queuing Network Concepts
19.2 Queuing Network Modules

Random Number Generator
A Package for Token and Arc Types
The Token Source Module
The Token Sink Module
The Queue Module
The Token Server Module
The Fork Module
The Join Module

19.3 A Queuing Network for a Disk System
Exercises

20.1 Predefined Attributes

Attributes of Scalar Types
Attributes of Array Types and Objects
Attributes of Signals
Attributes of Named Items

20.2 User-Defined Attributes

Attribute Declarations
Attribute Specifications
The Attribute Foreign

20.3 Groups
Exercises

21.1 Buffer and Linkage Ports
21.2 Conversion Functions in Association Lists
21.3 Postponed Processes
21.4 Shared Variables
Exercises

A.1 Synthesis Tools
A.2 A Synthesis Subset of VHDL

EVSWG Synthesis Subsets

A.3 Tricks and Hints

Using IEEE Standard 1164 Logic Types
Design Partitioning

A.4 The Draft P1076.3 Standard Synthesis Package
A.5 Examples-"Doing It Right"

Finite-State Machines

A.6 Examples-"Doing It Wrong"
A.7 Hand Instantiation-"Doing it the hard way"

D.1 IEEE Std. 1029.1: WAVES
D.2 IEEE P1076a: Shared Variables
D.3 IEEE P1076.1: VHDL-A-Analog Extensions to VHDL
D.4 IEEE P1076.2: Standard VHDL Language Mathematical Package
D.5 IEEE P1076.3: Standard VHDL Language Synthesis Package
D.6 IEEE P1076.4: Timing Methodology (VITAL)
D.7 IEEE P1076.5: VHDL Utility Library
D.8 IEEE P1165: EDIF Interoperability
D.9 EIA-567A: Component Modeling and Interface Standard

Index to Syntax Rules
E.1 Design File
E.2 Library Unit Declarations
E.3 Declarations and Specifications
E.4 Type Definitions
E.5 Concurrent Statements
E.6 Sequential Statements
E.7 Interfaces and Associations
E.8 Expressions

Lexical Differences
Syntactic Differences
Semantic Differences
Differences in the Standard Environment
VHDL-93 Facilities Not in VHDL-87