Introductory VHDL

Features

• Part of the Xilinx Design Series - Each copy comes with a free copy of the Xilinx Student Edition 2.1.
  
• Provides the reader with a complete learning package.
  
• Coverage of basic concepts.
  
• Provides students with tutorials, examples, and laboratory exercises to promote better understanding of language features.
  
• New integrated design environment from Xilinx - Available with the text and for its use in examples.
  
• Reinforces concepts and enables students to learn state-of-the-art technology.
  
• Dual approach.
  
• Shows synthesis and simulation as complementary facets of the use of VHDL.
  
• Examples and exercises in a CAD tool independent fashion - Xilinx specific descriptions available in Appendices.
  
• The understanding of language concepts is not impeded by CAD tool specific issues.
  
• Full set of viewgraphs and VHDL examples - Available on a Companion Website.
  
• Provides students with a visual presentation to reinforce text explanations.
  
• Coverage of basic simulation and synthesis concepts.
  
• Discrete event simulation and hardware inference are presented as the underlying models for simulation and synthesis. As a result students quickly generate an intuition about writing and debugging VHDL programs.
  
• Language constructs are presented by association with familiar concepts from digital logic and computer architecture.
  
• Language constructs are easier to grasp and apply in a short period of time.
  
• Departure from conventional pedagogy in teaching hardware description languages
  
• Emphasis is on providing a framework for thinking and reasoning about the structure and operation of VHDL programs. Students are productively constructing useful models very quickly.
  
• Presentation follows the VHDL 1993 standard.
  
• Skills are compliant with industry standard implementations.
  

Contents

• Preface
  
• Introduction
  
• Modeling Digital Systems
  
• Simulation vs. Synthesis
  
• Basic Language Concepts
  
• Basic Language Concepts: Synthesis
  
• Modeling Behavior: Simulation
  
• Modeling Behavior: Synthesis
  
• Modeling Structure
  
• Subprograms, Packages, and Libraries
  
• Basic Input/Output
  
• Programming Mechanics
  
• Identifiers
  
• Data Types, and Operators
  
• Standard VHDL Packages
  
• Index