The Designer's Guide to VHDL
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.
This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. Features:
- Details how the new standard allows for increased portability across tools.
- Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
- Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
- Packaged with a CD that accesses a VHDL Compiler and Simulator with Graphical Debugging from FTL Systems, and all the code for all the examples and case studies in the book.
- Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
- 1 Fundamental Concepts
- 2 Scalar Data Types and Operations
- 3 Sequential Statements
- 4 Composite Data Types and Operations
- 5 Basic Modeling Constructs
- 6 Case Study: A Pipelined Multiplier Accumulator
- 7 Subprograms
- 8 Packages and Use Clauses
- 9 Aliases
- 10 Case Study: A Bit-Vector Arithmetic Package
- 11 Resolved Signals
- 12 Generic Constants
- 13 Components and Configurations
- 14 Generate Statements
- 15 Case Study: The DLX Computer System
- 16 Guards and Blocks
- 17 Access Types and Abstract Data Types
- 18 Files and Input/Output
- 19 Case Study: Queuing Networks
- 20 Attributes and Groups
- 21 Miscellaneous Topics
- A Synthesis
- B The Predefined Package Standard
- C IEEE Standard Packages
- D Related Standards
- E VHDL Syntax
- F Differences
- G Answers to Exercises
- H Software Guide
L'auteur - Peter J. Ashenden
Dr. Peter Ashenden is a Senior Lecturer in Computer Science at the University of Adelaide. He received his B.Sc.(Hons) and Ph.D. from Adelaide. His research areas are computer organization and electronic design automation. He is actively involved in IEEE working groups developing VHDL standards, and is the author of The VHDL Cookbook, The Designer's Guide to VHDL and The Student's Guide to VHDL. He is a Senior Member of the IEEE, a member of the ACM, and co-series editor for the MKP Series on Systems on Silicon.
|Auteur(s)||Peter J. Ashenden|
|Nb. de pages||7759|
|Format||18,7 x 23,3|
|Intérieur||Noir et Blanc|
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