Memory Management for Synthesis of DSP Software

Praveen K. Murthy, Shuvra S. Bhattacharyya

300 pages, parution le 28/03/2006

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Résumé

Although programming in memory-restricted environments is never easy, this holds especially true for digital signal processing (DSP). The data-rich, computation-intensive nature of DSP makes memory management a chief and challenging concern for designers. Memory Management for Synthesis of DSP Software focuses on minimizing memory requirements during the synthesis of DSP software from dataflow representations. Dataflow representations are used in many popular DSP design tools, and the methods of this book can be applied in that context, as well as other contexts where dataflow is used.

This book systematically reviews research conducted by the authors on memory minimization techniques for compiling synchronous dataflow (SDF) specifications. Beginning with an overview of the foundations of software synthesis techniques from SDF descriptions, it examines aggressive buffer-sharing techniques that take advantage of specific and quantifiable tradeoffs between code size and buffer size to achieve high levels of buffer memory optimization.

The authors outline coarse-level strategies using lifetime analysis and dynamic storage allocation (DSA) for efficient buffer sharing as one approach and demonstrate the role of the CBP (consumed-before-produced) parameter at a finer level using a merging framework for buffer sharing. They present two powerful algorithms for combining these sharing techniques and then introduce techniques that are not restricted to the single appearance scheduling space of the other techniques.

Extensively illustrated to clarify the mathematical concepts, Memory Management for Synthesis of DSP Software presents a comprehensive survey of state-of-the-art research in DSP software synthesis.

Sommaire

Introduction
- Electronic Embedded Systems
- Digital Signal Processing Systems
- Actor-Oriented Design
- Dataflow MoCs for DSP Systems
- Synthesis Techniques in AOPEs
- Advances in Compilers for DSPs
- Other Related Work-Nested Loop Scheduling
Notation and Background
- Graph Terminology
- Synchronous Dataflow
- Synthesis from SDF Graphs
- Scheduling Problems for SDF Graphs
- Constructing Memory-Efficient Loop Structures
- Scheduling for Other Metrics
- Other Topics: Holes
- Summary
Lifetime Analysis
- Introduction
- The Shared Buffer Model
- Creating the Interval Instances from a SAS
- Conclusion
Dynamic Storage Allocation
- Some Notation
- Heuristic for DSA
- Computing the Maximum Clique Weight
- Experimental Results
- Approximation Algorithms
The CBP Parameter
- Related Work
- Introduction to Buffer Merging
- The CBP Parameter
- Multirate FIR Filters
- Chop
- Autocorrelation
- CBP Tables
- Summary of Derivations
- Conclusion
Buffer Sharing Via Merging Techniques
- Merging an Input/Output Buffer Pair
- Merging a Chain of Buffers
- A Heuristic for Merged Cost-Optimal SAS
- Conclusion
Buffer Merging Algorithms
- Acyclic Graphs
- Experimental Results
- Conclusion
Beyond Single Appearance Schedules
- Recursive Decomposition of a Two-Actor SDF Graph
- Extension to Arbitrary SAS
- CD-DAT Example
- Experimental Results
- Conclusion

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Caractéristiques techniques

	PAPIER
Éditeur(s)	Taylor and Francis Books
Auteur(s)	Praveen K. Murthy, Shuvra S. Bhattacharyya
Parution	28/03/2006
Nb. de pages	300
Format	16 x 24
Couverture	Relié
Poids	565g
Intérieur	Noir et Blanc
EAN13	9780849337529
ISBN13	978-0-8493-3752-9