VLSI Test Principles and Architectures
Design for Testability
Laung-Terng Wang, Xiaoqing Wen, Cheng-Wen Wu - Collection Systems on Silicon
Résumé
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
Features & Benefits
- Most up-to-date coverage of design for testability.
- Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
- Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
- Lecture slides for Chapters 1-5 and exercise solutions for Chapters 1, 2, 3 & 5 are available now.
- Lecture slides and exercise solutions for the remaining chapters will be available by September 15, 2006.
Sommaire
- Introduction
- Design for Testability
- Logic and Fault Simulation
- Test Generation
- Logic Built-In Self-Test
- Test Compression
- Logic Diagnosis
- Memory Testing and Built-In Self-Test
- Memory Diagnosis and Built-In Self-Repair
- Boundary Scan and Core-Based Testing
- Analog and Mixed-Signal Testing
- Test Technology Trends in the Nanometer Age
Caractéristiques techniques
PAPIER | |
Éditeur(s) | Morgan Kaufmann |
Auteur(s) | Laung-Terng Wang, Xiaoqing Wen, Cheng-Wen Wu |
Collection | Systems on Silicon |
Parution | 11/09/2006 |
Nb. de pages | 800 |
Format | 20 x 24,5 |
Couverture | Relié |
Poids | 1795g |
Intérieur | Noir et Blanc |
EAN13 | 9780123705976 |
ISBN13 | 978-0-12-370597-6 |
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